#ifndef SCF_RISC_UTIL_H
#define SCF_RISC_UTIL_H

#include"scf_def.h"

enum scf_risc_OpCode_types {
	SCF_RISC_MOV		= 0,

	SCF_RISC_MOVSX,
	SCF_RISC_MOVZX,

	SCF_RISC_MOVS,
	SCF_RISC_STOS,

	SCF_RISC_LEA,

	SCF_RISC_PUSH,
	SCF_RISC_POP,

	SCF_RISC_INC,
	SCF_RISC_DEC,

	// 10
	SCF_RISC_XOR,
	SCF_RISC_AND,
	SCF_RISC_OR,
	SCF_RISC_NOT,

	SCF_RISC_NEG,

	// 15
	SCF_RISC_CALL,
	SCF_RISC_RET,

	SCF_RISC_ADD,
	SCF_RISC_SUB,

	SCF_RISC_MUL,
	SCF_RISC_DIV,

	// 21
	SCF_RISC_IMUL,
	SCF_RISC_IDIV,

	// sign-extend ax to dx:ax
	SCF_RISC_CBW,
	SCF_RISC_CWD = SCF_RISC_CBW,
	SCF_RISC_CDQ = SCF_RISC_CBW,
	SCF_RISC_CQO = SCF_RISC_CBW,

	// 24
	SCF_RISC_SAR,
	SCF_RISC_SHR,
	SCF_RISC_SHL,

	SCF_RISC_CMP,
	SCF_RISC_TEST,

	SCF_RISC_SETZ,
	SCF_RISC_SETNZ,

	// 31
	SCF_RISC_SETG,
	SCF_RISC_SETGE,

	SCF_RISC_SETL,
	SCF_RISC_SETLE,

	SCF_RISC_ADDSS,
	SCF_RISC_ADDSD,

	SCF_RISC_SUBSS,
	SCF_RISC_SUBSD,

	SCF_RISC_MULSS,
	SCF_RISC_MULSD,

	// 41
	SCF_RISC_DIVSS,
	SCF_RISC_DIVSD,

	SCF_RISC_MOVSS,
	SCF_RISC_MOVSD,

	SCF_RISC_UCOMISS,
	SCF_RISC_UCOMISD,

	// 47
	SCF_RISC_CVTSI2SD,
	SCF_RISC_CVTSI2SS,

	SCF_RISC_CVTSS2SD,
	SCF_RISC_CVTSD2SS,

	SCF_RISC_CVTTSD2SI,
	SCF_RISC_CVTTSS2SI,

	SCF_RISC_PXOR,

	SCF_RISC_JZ,
	SCF_RISC_JNZ,

	SCF_RISC_JG,
	SCF_RISC_JGE,

	SCF_RISC_JL,
	SCF_RISC_JLE,

	SCF_RISC_JA,
	SCF_RISC_JAE,

	SCF_RISC_JB,
	SCF_RISC_JBE,

	SCF_RISC_JMP,

	SCF_RISC_NB
};

enum scf_risc_REGs {
	SCF_RISC_REG_W0 = 0,
	SCF_RISC_REG_X0 = 0,
	SCF_RISC_REG_S0 = 0,
	SCF_RISC_REG_D0 = 0,

	SCF_RISC_REG_W1 = 1,
	SCF_RISC_REG_X1 = 1,
	SCF_RISC_REG_S1 = 1,
	SCF_RISC_REG_D1 = 1,

	SCF_RISC_REG_W2 = 2,
	SCF_RISC_REG_X2 = 2,
	SCF_RISC_REG_S2 = 2,
	SCF_RISC_REG_D2 = 2,

	SCF_RISC_REG_W3 = 3,
	SCF_RISC_REG_X3 = 3,
	SCF_RISC_REG_S3 = 3,
	SCF_RISC_REG_D3 = 3,

	SCF_RISC_REG_W4 = 4,
	SCF_RISC_REG_X4 = 4,
	SCF_RISC_REG_S4 = 4,
	SCF_RISC_REG_D4 = 4,

	SCF_RISC_REG_W5 = 5,
	SCF_RISC_REG_X5 = 5,
	SCF_RISC_REG_S5 = 5,
	SCF_RISC_REG_D5 = 5,

	SCF_RISC_REG_W6 = 6,
	SCF_RISC_REG_X6 = 6,
	SCF_RISC_REG_S6 = 6,
	SCF_RISC_REG_D6 = 6,

	SCF_RISC_REG_W7 = 7,
	SCF_RISC_REG_X7 = 7,
	SCF_RISC_REG_S7 = 7,
	SCF_RISC_REG_D7 = 7,

	SCF_RISC_REG_W8 = 8,
	SCF_RISC_REG_X8 = 8,

	SCF_RISC_REG_W9 = 9,
	SCF_RISC_REG_X9 = 9,

	SCF_RISC_REG_W10 = 10,
	SCF_RISC_REG_X10 = 10,

	SCF_RISC_REG_W11 = 11,
	SCF_RISC_REG_X11 = 11,

	SCF_RISC_REG_W12 = 12,
	SCF_RISC_REG_X12 = 12,

	SCF_RISC_REG_W13 = 13,
	SCF_RISC_REG_X13 = 13,

	SCF_RISC_REG_W14 = 14,
	SCF_RISC_REG_X14 = 14,

	SCF_RISC_REG_W15 = 15,
	SCF_RISC_REG_X15 = 15,

	SCF_RISC_REG_W16 = 16,
	SCF_RISC_REG_X16 = 16,

	SCF_RISC_REG_W17 = 17,
	SCF_RISC_REG_X17 = 17,

	SCF_RISC_REG_W18 = 18,
	SCF_RISC_REG_X18 = 18,

	SCF_RISC_REG_W19 = 19,
	SCF_RISC_REG_X19 = 19,

	SCF_RISC_REG_W20 = 20,
	SCF_RISC_REG_X20 = 20,

	SCF_RISC_REG_W21 = 21,
	SCF_RISC_REG_X21 = 21,

	SCF_RISC_REG_W22 = 22,
	SCF_RISC_REG_X22 = 22,

	SCF_RISC_REG_W23 = 23,
	SCF_RISC_REG_X23 = 23,

	SCF_RISC_REG_W24 = 24,
	SCF_RISC_REG_X24 = 24,

	SCF_RISC_REG_W25 = 25,
	SCF_RISC_REG_X25 = 25,

	SCF_RISC_REG_W26 = 26,
	SCF_RISC_REG_X26 = 26,

	SCF_RISC_REG_W27 = 27,
	SCF_RISC_REG_X27 = 27,

	SCF_RISC_REG_W28 = 28,
	SCF_RISC_REG_X28 = 28,

	SCF_RISC_REG_X29 = 29,
	SCF_RISC_REG_FP  = 29,

	SCF_RISC_REG_X30 = 30,
	SCF_RISC_REG_LR  = 30,

	SCF_RISC_REG_SP  = 31,
};

enum scf_risc_EG_types {
	SCF_RISC_G	= 0,
	SCF_RISC_I	= 1,
	SCF_RISC_G2E	= 2,
	SCF_RISC_E2G = 3,
	SCF_RISC_I2E = 4,
	SCF_RISC_I2G = 5,
	SCF_RISC_E	= 6,
};

#endif

